Specification

Everything you need to know about the hardware, plus the low-level details for writing your own driver.

Hardware

Software support

GPIO pins

SPI settings

Data frame

Each chip delivers a 27-byte frame per sample:

Chip 1 gives channels 1–8, chip 2 gives channels 9–16. Each channel is a 24-bit, big-endian, two's-complement value. The SDK only accepts a sample when chip 2's status word is 0xC0 0x00 0x08, which filters out bad frames.

Converting to microvolts

This is the conversion used by the PiEEG SDK scripts and PiEEG Server:

raw = (b[0] << 16) | (b[1] << 8) | b[2]   # 3 bytes of one channel
if raw & 0x800000:                       # negative value
    raw -= 16777214
uV = raw * 4.5 / 16777215 * 1_000_000    # about 0.268 µV per count

Reading a sample

import spidev, gpiod                      # gpiod==1.5.4
 
chip = gpiod.chip("0")                    # see the GPIO chip table above
cs2 = chip.get_line(19)                   # chip select for ADS1299 #2
# ... request cs2 as output (high), DRDY 26 and 13 as inputs,
#     open spi1 = spidev 0.0 and spi2 = spidev 0.1 (mode 1),
#     configure both chips (see below), then for every sample:
 
wait_for_drdy(drdy1)                      # wait for GPIO 26 high → low
frame1 = spi1.readbytes(27)               # channels 1–8
 
wait_for_drdy(drdy2)                      # wait for GPIO 13 high → low
cs2.set_value(0)
frame2 = spi2.readbytes(27)               # channels 9–16
cs2.set_value(1)

Full working version: pieeg16_drdy_only.py (opens in a new tab).

ADS1299 commands

Write a register with three bytes: [0x40 | address, 0x00, value]. Read one with [0x20 | address, 0x00, 0x00]. For chip 2, pull GPIO 19 low around each transfer.

Default register settings

Both chips get the same settings. Start-up sequence used by PiEEG software, chip 1 first, then chip 2: WAKEUP, STOP, RESET, SDATAC, write the registers below, then RDATAC and START.