Hardware
Devices
JNEEG
Electrodes & Pinout

Electrodes & Pinout

Electrode connections

JNEEG has three kinds of electrode inputs.

InputCountElectrodePurpose
Channels 1–88Dry or wet Ag/AgCl, in the capEach channel measures the voltage between its electrode and the reference
Reference1Ear clip on one earlobeThe common 0 µV point that all 8 channels are measured against
Bias1Ear clip on the other earlobeActively drives the body to cancel common-mode noise such as 50/60 Hz mains hum

JNEEG: electrodes, reference and bias on the 2.54 mm header; ADS1299, regulators, status LED and 40-pin header

The electrode header is a standard 2.54 mm pin header (marked 1-8 Elec), so most EEG cables with 2.54 mm female connectors fit. See Cap.

The reference and bias clips matter most. A loose ear clip makes every channel noisy at once. Clean the earlobes and make sure both clips sit firmly.

Suggested montage

Place the electrodes on the 10-20 system. This layout is the same as the PiEEG-8 default, so recordings can be compared:

ChannelPositionAreaGood for
1Fp1Front leftBlinks, eye movement
2Fp2Front rightBlinks, eye movement
3C3Centre leftMotor activity (right hand)
4C4Centre rightMotor activity (left hand)
5P7Back left, sideParietal and temporal activity
6P8Back right, sideParietal and temporal activity
7O1Back leftAlpha rhythm, vision
8O2Back rightAlpha rhythm, vision

International 10-20 electrode positions

You can use any other positions. Keep a note of which channel went where.

Jetson Nano pinout

The shield talks to the Jetson Nano over SPI (spi1 in jetson-io, which appears as /dev/spidev0.0). It uses these pins on the 40-pin header:

Header pinSignalDirection
19SPI MOSIJetson → ADS1299
21SPI MISOADS1299 → Jetson
23SPI SCKJetson → ADS1299
24SPI CS0 (chip select)Jetson → ADS1299
7DRDY (data ready)ADS1299 → Jetson

The shield also takes its power and ground from the header.

DRDY goes low each time a new sample is ready (250 times per second). The Python scripts read it as board pin 7 with Jetson.GPIO. PiEEG Server reads it as line 216 on /dev/gpiochip0.